Method of hybrid high-k/metal-gate stack fabrication

摘要

A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate.

主权项

1. A process for fabricating a semiconductor device, the process comprising:
providing a semiconductor substrate with a plurality of isolation features and a first high-k (HK) dielectric material; forming first, second, and third polysilicon gate stacks on the semiconductor substrate; forming sidewall spacers on the polysilicon gate stacks; forming a source and a drain on the semiconductor substrate; forming an interlayer dielectric (ILD) layer on the semiconductor substrate; performing a chemical mechanical planarization (CMP) on the ILD layer; forming a patterned hard mask on the first polysilicon gate stacks to define a high-resistor on the semiconductor substrate; patterning and defining an n-type field-effect transistor (NFET) region with the second polysilicon gate stack and a p-type field-effect transistor (PFET) region with the third polysilicon gate stack on the semiconductor substrate; performing a first gate etch to partially remove the third polysilicon gate stack in the PFET region; after the first gate etch, exposing both the NFET region, the PFET region and the high-resistor; performing a second gate etch to partially remove the second polysilicon gate stack in the NFET region to form a NFET gate trench; and removing polysilicon in the PFET region to form a PFET gate trench; and removing the patterned hard mask on the first polysilicon gate stack; filling both the PFET and the NFET gate trenches with a second HK dielectric material; depositing a p-type work function (p-WF) metal on the second HK dielectric material on both of the PFET and the NFET gate trenches; depositing a filling metal layer on the p-WF metal layer; performing a metal CMP to remove excessive metal layer and excess second HK dielectric material to form HK/metal gate stacks in the NFET and PFET regions.