发明名称 Method of forming nonvolatile memory device
摘要 A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.
申请公布号 US9093479(B2) 申请公布日期 2015.07.28
申请号 US201314074817 申请日期 2013.11.08
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Son Byoungkeun;Lee Changhyun;Lee Jaegoo;Seol Kwang Soo;You Byungkwan
分类号 H01L29/72;H01L29/792;H01L29/66;H01L27/115 主分类号 H01L29/72
代理机构 Lee & Morse, P.C. 代理人 Lee & Morse, P.C.
主权项 1. A method of forming a nonvolatile memory device, the method comprising: providing a semiconductor substrate; repeatedly and alternately stacking sacrificial layers and inter-gate dielectric layers on the semiconductor substrate; forming an active pillar that penetrates the inter-gate dielectric layers and the sacrificial layers to contact the semiconductor substrate; patterning the inter-gate dielectric layers and the sacrificial layers at a position spaced from the active pillar to form a first opening; removing the sacrificial layers through the first opening; and forming a gate pattern on a region where the sacrificial layers are removed, wherein a corner of the gate pattern adjacent to the active pillar is formed to be rounded, wherein forming the active pillar includes: patterning the inter-gate dielectric layers and the sacrificial layers to form a second opening;conformally forming an auxiliary insulating layer, a gate insulating layer and a first semiconductor layer on the semiconductor substrate where the second opening is formed;performing an anisotropic etching process on the first semiconductor layer, the gate insulating layer, and the auxiliary insulating layer to form an auxiliary insulating pattern, a gate insulating pattern, and a first semiconductor pattern covering a sidewall of the second opening; andforming a second semiconductor layer covering the semiconductor substrate exposed through the second opening and a sidewall of the first semiconductor pattern, and wherein the second semiconductor layer and the first semiconductor pattern constitute the active pillar.
地址 Suwon-si, Gyeonggi-do KR