Time-to-digital converter

摘要

Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.

主权项

1. A time-to-digital converter, comprising:
a ring oscillator circuit configured to produce phase signals; a counter circuit configured to count oscillations of the ring oscillator circuit; a sampling circuit configured to capture values of the phase signals based on a stop signal, the sampling circuit including master latches enabled based on the stop signal, each of the master latches having an input coupled to one of the phase signals; and a clock generation circuit configured to produce a counter clock signal for triggering the counter circuit based on two or more outputs of the master latches, respectively.