Completing middle of line integration allowing for self-aligned contacts

摘要

In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET having complete middle of line integration. Specifically, a hard mask layer and set of spacers are removed from the gate stacks leaving behind (among other things) a set of dummy gates. A liner layer is formed over the set of dummy gates and over a source-drain region adjacent to the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates and the source-drain region. An inter-layer dielectric (ILD) is then deposited over the set of dummy gates and over the source-drain region, and the set of dummy gates are then removed. The result is an environment in which a self-aligned contact to the source-drain region can be deposited.

主权项

1. A method for completing middle of line integration in a semiconductor device, comprising:
removing a hard mask layer and a set of spacers from a set of dummy gates; depositing a liner layer over the set of dummy gates and over a source-drain region adjacent to the set of dummy gates subsequent to removing the hard mask layer and set of spacers; removing the liner layer from at least a portion of a top surface of the set of dummy gates and from at least a portion of a top surface of the source-drain region; depositing an inter-layer dielectric (ILD) over the set of dummy gates and over the source-drain region subsequent to the removing of the liner layer, and removing the set of dummy gates.