Systems and methods for faster throughput for compressed video data decoding

摘要

Presented herein are system(s) and method(s) for faster throughput for video decoding. In one embodiment, there is presented a pixel reconstructor for generating reconstructed pixels. The pixel reconstructor comprises a SIMD processor, a data access unit, and a circuit. The SIMD processor applies at least one prediction error to at least one block of prediction pixels. The data access unit provides the at least one prediction error and the at least one block of prediction pixels. A circuit determines whether two or more prediction errors and two or more prediction pixels can be concurrently processed by the SIMD processor.

主权项

1. A system comprising:
a single instruction, multiple data (SIMD) processor, the SIMD processor comprising an instruction memory for storing a set of instructions and a plurality of processing elements configured to concurrently execute an instruction from the set of instructions on a corresponding plurality of pixels from a row in at least one prediction error and a corresponding plurality of pixels from a row in at least one block of prediction pixels; and a data access circuitry for providing the at least one prediction error and the at least one block of prediction pixels; and a circuit for determining whether two or more prediction errors and two or more prediction pixels can be concurrently processed by the SIMD processor.