发明名称 |
BUS CONTROL CIRCUIT, INFORMATION PROCESSOR, AND COMMON BUS COLLISION AVOIDANCE METHOD |
摘要 |
<p>PROBLEM TO BE SOLVED: To prevent an abnormality of one of a plurality of control circuits from causing a situation in which a normal control circuit cannot use a common bus.SOLUTION: The bus control circuit 1 includes an abnormality detection circuit 2 and an adjusting circuit 3. The abnormality detection circuit 2 detects the abnormality of bus control signals S1 and S2 for reporting whether control circuits 5 and 6 demand the use of a common bus 7. The adjusting circuit 3 includes a logic circuit for creating a signal for controlling the flow of data D1 and D2 from respective control circuits 5 and 6 to the common bus 7 on the basis of the bus control signals S1 and S2 output from respective control circuits 5 and 6, presence/absence of abnormality detection by the abnormality detection circuit 2, and a previously determined priority of use of the common bus 7.</p> |
申请公布号 |
JP2015135599(A) |
申请公布日期 |
2015.07.27 |
申请号 |
JP20140006774 |
申请日期 |
2014.01.17 |
申请人 |
NEC ENGINEERING LTD |
发明人 |
MANO NORIHITO |
分类号 |
G06F13/36;G06F13/362;G06F13/42 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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