| 摘要 |
<p>PROBLEM TO BE SOLVED: To design a clock path that is excellent in resistance properties with respect to power source noise.SOLUTION: A design device 1 is configured to: preferentially select a small coefficient within a range satisfying a design condition from a coefficient group (coefficent library 5) showing delay increase when a voltage falls for each combination of clock buffers 11a, 11b and 11c different in a parameter and wiring loads 12a, 12b and 12c connected to the clock buffers 11a, 11b and 11c; select the clock buffer and wiring load that have a parameter associated with the selected coefficient out of the clock buffers 11a, 11b and 11c and wiring loads 12a, 12b and 12c, and design a clock path 10.</p> |
