| 摘要 |
<p>A link signal synchronization circuit is disclosed. According to an aspect of the present invention, when processing signals sent from PHYs of each lane for a sink device of display port to a link, the present invention provides a link signal synchronization circuit which integrates a process of bit alignment and clock unification for each lane, and word data synchronization between lanes and de-skewing. According to the present invention, the processes of sending signals from PHYs of each lane for the sink device are integrated as one; thereby the number of gates necessary for synchronization is reduced, and implementation of a lower power consuming link circuits can be achieved.</p> |
