发明名称 SYSTEMS AND METHODS FOR ENCODING AND DECODING OF CHECK-IRREGULAR NON-SYSTEMATIC IRA CODES
摘要 Systems and methods for encoding and decoding check-irregular non-systematic IRA codes of messages in any communication or electronic system where capacity achieving coding is desired. According to these systems and methods, IRA coding strategies, including ones that employ capacity-approaching non-systematic IRA codes that are irregular and that exhibit a low error floor, are employed. These non-systematic IRA codes are particularly advantageous in scenarios in which up to half of coded bits could be lost due to channel impairments and/or where complementary coded bits are desired to transmit over two or more communications sub-channels. An encoder includes information bit repeaters and encoders, one or more interleavers, check node combiners, a check node by-pass and an accumulator. A decoder includes a demapper, one or more check node processors, an accumulator decoder, a bit decoder, and one or more interleavers/deinterleavers.
申请公布号 US2015207524(A1) 申请公布日期 2015.07.23
申请号 US201514607043 申请日期 2015.01.27
申请人 Digital PowerRadio, LLC 发明人 Vojcic Branimir R.;Papaharalabos Stylianos
分类号 H03M13/11;H03M13/00 主分类号 H03M13/11
代理机构 代理人
主权项 1. A system for encoding check-irregular non-systematic irregular repeat accumulate codes, the system comprising: at least one information bit repeater having at least one degree, wherein each of the at least one information bit repeaters produces identical replicas of an information bit based on the degree of the information bit repeater, the at least one information bit repeater producing a first set of coded bits; an interleaver that interleaves the first set of coded bits and produces a second set of coded bits; a set of check node combiners of different degrees, wherein a check node combiner with a degree M greater than or equal to 2 performs modulo 2-addition on M information bits, and a check node combiner with a degree M equal to 1 bypasses the modulo 2-addition, wherein the set of check node combiners produces a third set of coded bits from the second set of coded bits; and a convolutional encoder for encoding the third set of coded bits, wherein the output of the convolutional encoder is a check-irregular non-systematic irregular repeat accumulate code.
地址 Palm Beach FL US