| 发明名称 |
MULTI-CORE ARCHITECTURE FOR LOW LATENCY VIDEO DECODER |
| 摘要 |
An apparatus having first, second and third processors of a multi-core processor is disclosed. The first processor is configured to perform one or more first operations in a decoding of a plurality of macroblocks of video in a bitstream. The second processor (i) operates as a slave to the first processor and (ii) is configured to perform one or more second operations in the decoding of the macroblocks. The third processor (i) operates as a slave to the second processor and (ii) is configured to perform one or more third operations in the decoding of the macroblocks. |
| 申请公布号 |
US2015208076(A1) |
申请公布日期 |
2015.07.23 |
| 申请号 |
US201414174183 |
申请日期 |
2014.02.06 |
| 申请人 |
LSI Corporation |
发明人 |
Tan Mizhou;Barazesh Bahman |
| 分类号 |
H04N19/436 |
主分类号 |
H04N19/436 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a first processor of a multi-core processor configured to perform one or more first operations in a decoding of a plurality of macroblocks of video in a bitstream; a second processor of said multi-core processor (i) operating as a slave to said first processor and (ii) configured to perform one or more second operations in said decoding of said macroblocks; and a third processor of said multi-core processor (i) operating as a slave to said second processor and (ii) configured to perform one or more third operations in said decoding of said macroblocks. |
| 地址 |
San Jose CA US |
