CLOCK CONTROLLER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

摘要

A dock controller may include a dock period detector suitable for delaying a first dock signal through a plurality of unit delay circuits, and outputting a detection signal by detecting a period of the first dock signal as the number of unit delay circuits used for unit delay of the first clock signal among the unit delay circuits; and a clock generator suitable for generating a delay clock signal delayed by a half period of the first dock signal in response to the detection signal outputted from the clock period detector, and generating a second clock signal having a period corresponding to edges of the first clock signal and the delay clock signal.

主权项

1. A clock controller comprising:
a dock period detector suitable for delaying a first clock signal through a plurality of unit delay circuits, and outputting a detection signal by detecting a period of the first clock signal as the number of unit delay circuits used for unit delay of the first clock signal among the unit delay circuits; and a clock generator suitable for generating a delay clock signal delayed by a half period of the first clock signal in response to the detection signal outputted from the clock period detector, and generating a second clock signal having a period corresponding to edges of the first clock signal and the delay clock signal.