| 发明名称 |
LOW-POWER DUAL QUANTIZATION-DOMAIN DECODING FOR LDPC CODES |
| 摘要 |
A low density parity check decoder is provided that includes a variable-node (VN) processing domain comprising high-bit resolution processing circuitry, a check-node (CN) processing domain comprising low-bit resolution processing circuitry lower than the high-bit resolution processing circuitry, and mapping circuitry configured to transfer a message between the VN processing domain and the CN processing domain. |
| 申请公布号 |
US2015207523(A1) |
申请公布日期 |
2015.07.23 |
| 申请号 |
US201514599325 |
申请日期 |
2015.01.16 |
| 申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Abu-Surra Shadi;Pisek Eran;Henige Thomas Michael;Rajagopal Sridhar |
| 分类号 |
H03M13/11 |
主分类号 |
H03M13/11 |
| 代理机构 |
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代理人 |
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| 主权项 |
1. A low density parity check (LDPC) decoder, comprising:
a variable-node (VN) processing domain comprising high-bit resolution processing circuitry; a check-node (CN) processing domain comprising low-bit resolution processing circuitry lower than the high-bit resolution processing circuitry; and mapping circuitry configured to transfer a message between the VN processing domain and the CN processing domain. |
| 地址 |
Suwon-si KR |
