| 发明名称 |
DIGITAL PHASE-LOCKED LOOP (DPLL), METHOD OF CONTROLLING DPLL, AND ULTRA LOW POWER (ULP) TRANSCEIVER USING DPLL |
| 摘要 |
A phase-locked loop (PLL) includes a counter configured to measure voltage-controlled oscillator (VCO) information of an oscillator during a mask time, and a frequency tuner configured to tune a frequency of the oscillator to a target frequency, based on a comparison result obtained by comparing the VCO information to target frequency information. |
| 申请公布号 |
US2015207514(A1) |
申请公布日期 |
2015.07.23 |
| 申请号 |
US201514600533 |
申请日期 |
2015.01.20 |
| 申请人 |
Samsung Electronics Co., Ltd. ;Research & Business Foundation Sungkyunkwan University |
发明人 |
KIM Seong Joong;YUN Seok Ju;HONG Young Jun;PARK Hyung Gu;LEE Kang Yoon |
| 分类号 |
H03L7/099;H04B1/40 |
主分类号 |
H03L7/099 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A phase-locked loop (PLL), comprising:
a counter configured to measure voltage-controlled oscillator (VCO) information of an oscillator during a mask time; and a frequency tuner configured to tune a frequency of the oscillator to a target frequency, based on a comparison result obtained by comparing the VCO information to target frequency information. |
| 地址 |
Suwon-si KR |
