DETERMINISTIC FIFO BUFFER

摘要

One embodiment relates to a method for determining a latency of a FIFO buffer. A highest-order bit is provided from FIFO write and read counters to input-comparison logic that distinguishes between the highest-order write and read bits having a same logic level and the highest-order write and read bits having different logic levels. The occupancy level, and hence the latency, of the FIFO buffer is determined based on the output of the input-comparison logic. Another embodiment relates to a FIFO buffer having write and read counters that each have a length in bits that is one bit longer than is needed to address the FIFO buffer. Another embodiment relates to a method of tuning a latency of a FIFO buffer. Other embodiments and features are also disclosed.

主权项

1. A method for determining an average latency of a first-in-first-out buffer, the method comprising:
applying input-comparison logic to a first input comprising a highest-order read bit from a read counter and a second input comprising a highest-order write bit from a write counter, wherein the input-comparison logic differentiates between the first and second inputs having a same logic level and the first and second inputs having different logic levels; generating an output signal by the input-comparison logic; and determining an occupancy level of the first-in-first-out buffer based on the output signal from the input-comparison logic.