发明名称 命令制御回路、プロセッサ、及び命令制御方法
摘要 In a vector processing device, a data dependence detecting unit detects a data dependence relation between a preceding instruction and a succeeding instruction which are inputted from an instruction buffer, and an instruction issuance control unit controls issuance of an instruction based on a detection result thereof. When there is a data dependence relation between the preceding instruction and the succeeding instruction, the instruction issuance control unit generates a new instruction equivalent to processing related to a vector register including the data dependence relation with the succeeding instruction in processing executed by the preceding instruction and issues the new instruction between the preceding instruction and the succeeding instruction, and thereby a data hazard can be avoided between the preceding instruction and the succeeding instruction without making a stall occur.
申请公布号 JP5751181(B2) 申请公布日期 2015.07.22
申请号 JP20120012250 申请日期 2012.01.24
申请人 富士通セミコンダクター株式会社 发明人 西川 建司
分类号 G06F17/16;G06F9/318;G06F9/38 主分类号 G06F17/16
代理机构 代理人
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