LDPC decoding using different quantization for check node and variable node processing
摘要
A low density parity check decoder is provided that includes a variable-node (VN) processing domain comprising high-bit resolution (high-precision quantisation) processing circuitry, a check-node (CN) processing domain comprising low-bit resolution (low-precision quantisation) processing circuitry lower than the high-bit resolution processing circuitry, and mapping circuitry configured to transfer a message between the VN processing quantisation domain and the CN processing quantisation domain.
申请公布号
EP2897294(A1)
申请公布日期
2015.07.22
申请号
EP20150151975
申请日期
2015.01.21
申请人
SAMSUNG ELECTRONICS CO., LTD
发明人
ABU-SURRA, SHADI;PISEK, ERAN;HENIGE, THOMAS MICHAEL;RAJAGOPAL, SRIDHAR