发明名称 Method for wafer level packaging and a package structure thereof
摘要 The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.
申请公布号 US9087912(B2) 申请公布日期 2015.07.21
申请号 US201414198493 申请日期 2014.03.05
申请人 CHIPMOS TECHNOLOGIES INC. 发明人 Liao Tsung Jen
分类号 H01L23/48;H01L23/00 主分类号 H01L23/48
代理机构 代理人 Shih Chun-Ming
主权项 1. A method for wafer level packaging, comprising: providing a first wafer including a surface, wherein a dielectric layer and a first conducting pillar are disposed on the surface and the first conducting pillar is configured to penetrate through the dielectric layer; singulating the first wafer to form a first die; forming a through hole in an interposer, wherein the interposer includes a first surface and a second surface opposite to the first surface, and a thickness of the interposer is less than or equal to a length of the first conducting pillar; disposing the first wafer on the first surface of the interposer and disposing the first conducting pillar inside the through hole; covering an encapsulation layer on the first die and a portion of the interposer; coating a first electric insulation layer on the second surface of the interposer; forming a redistribution layer on the first electric insulation layer, wherein the redistribution layer is electrically coupled to the first conducting pillar; anddisposing a solder ball on the redistribution layer.
地址 Hsinchu TW