Memory with merged control input

摘要

Chip selection and internal clocking functions are enabled within an integrated circuit memory component in response to a single “chip-enable” control signal, thus reducing memory system pin count and wiring complexity relative to designs that require separate chip-select and clock-enable signals. Internal clocking logic may also be provided to generate timing signal edges more precisely limited to the number required to complete a given memory component operation, reducing the number of unnecessary timing events and lowering power consumption. Further, internal read and write clock signals may be speculatively enabled within the memory component to more quickly stabilize those clocks in preparation for data transmission and reception operations, potentially lowering memory access latency.

主权项

1. An integrated circuit memory component comprising:
first logic to assert a chip-select signal in response to detecting a transition of an externally-generated control signal and to enable a predetermined number of transitions of a timing signal in response to detecting the transition of the externally-generated control signal; second logic to decode a command in response to assertion of the chip-select signal; and circuitry to perform operations indicated by the command at respective times indicated by respective transitions of the timing signal.