Semiconductor device, semiconductor wafer and manufacturing method of semiconductor device

摘要

A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

主权项

1. A semiconductor device comprising:
a semiconductor substrate that includes a scribe region and a chip region; a plurality of wiring layers formed over said semiconductor substrate; a via-layer interposed between said plurality of wiring layers; conductive films formed respectively in said plurality of wiring layers; and a via-plug disposed in said via-layer such that said via-plug connects said conductive films of said wiring layers respectively above and below said via-layer with each other, wherein said scribe region is located at an outer periphery of said chip region along an edge of said semiconductor substrate, said scribe region includes a pad region in the vicinity of said edge, said pad region overlaps with said conductive films of said plurality of wiring layers in a plan view, said plurality of wiring layers includes a first wiring layer and a second wiring layer, said conductive film of said first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, said conductive film of said second wiring layer includes a second conductive pattern formed in an outer periphery part of said pad region and a plurality of third conductive patterns disposed inside said pad region with a mutual separation, wherein said third conductive patterns are electrically isolated from said second conductive pattern.