发明名称 Method for measuring capacitances of capacitors
摘要 A capacitor measurement circuit for measuring a capacitance of a test capacitor includes a first transistor with a first source-drain path coupled between a first capacitor plate of the test capacitor and a ground; a second transistor with a second source-drain path coupled between a second capacitor plate of the test capacitor and the ground; and a current-measuring device configured to measure a first charging current and a second charging current of the test capacitors. The first and the second charging currents flow to the test capacitor in opposite directions.
申请公布号 US9086450(B2) 申请公布日期 2015.07.21
申请号 US201012897150 申请日期 2010.10.04
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Liu Min-Tar;Chang Chih-Chiang;Chen Chu-Fu;Huang Ping-Hsiang
分类号 G01R27/26;G01R31/28;H03K17/96 主分类号 G01R27/26
代理机构 Slater & Matsil, L.L.P. 代理人 Slater & Matsil, L.L.P.
主权项 1. A capacitor measurement circuit for measuring a capacitance of a test capacitor, the capacitor measurement circuit comprising: a first NMOS transistor with a first source-drain path coupled between a first capacitor plate of the test capacitor and a ground; a second NMOS transistor with a second source-drain path coupled between a second capacitor plate of the test capacitor and the ground; a current-measuring device configured to measure a first charging current and a second charging current of the test capacitor, wherein the first and the second charging currents flow to the test capacitor in opposite directions; a first PMOS transistor comprising a source coupled to the current-measuring device, and a drain coupled to a drain of the first NMOS transistor; a second PMOS transistor comprising a source coupled to the current-measuring device, and a drain coupled to a drain of the second NMOS transistor; and a control circuit configured to provide first non-overlay clock-cycle signals to gates of the first PMOS transistor and the first NMOS transistor, and second non-overlay clock-cycle signals to gates of the second PMOS transistor and the second NMOS transistor, wherein the first non-overlay clock-cycle signals are configured to turn on at most one of the first PMOS transistor and the first NMOS transistor, and the second non-overlay clock-cycle signals are configured to turn on at most one of the second PMOS transistor and the second NMOS transistor.
地址 Hsin-Chu TW