Adjusting bit reliability information input for decoding stored data

摘要

The present disclosure includes systems and techniques relating to adjusting bit reliability information input for decoding data stored in a memory device. In some implementations, an apparatus, systems, or methods can include a memory controller that includes circuitry configured to receive data from a memory device, where the data includes at least first and second states; circuitry configured to compare a number of the first and second states of the received data; and circuitry configured to adjust a bit reliability information input to a decoder based, at least in part, on the comparison.

主权项

1. A memory controller comprising:
circuitry configured to receive data from a memory device, the data comprising at least first and second states; circuitry configured to compare a number of the first and second states of the received data; and circuitry configured to adjust a bit reliability information input to a decoder based, at least in part, on the comparison; wherein the comparison provides a first delta, the memory controller further comprises circuitry configured to extract a second delta of first and second states, the second delta having been programmed into the memory device along with the data, and the circuitry configured to adjust comprises circuitry configured to compare the first delta and the second delta to adjust the reliability information input.