Advanced processor with interfacing messaging network to a CPU

摘要

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

主权项

1. A processor, comprising:
a messaging network; and a plurality of processor cores coupled to the messaging network, the plurality of processor cores having a plurality of respective designated portions configured to execute a plurality of software executable instructions to interface with the messaging network; wherein the messaging network is configured to be operated, based on the plurality of software executable instructions, to pass a packet between a processor core of the plurality of processor cores and other processor cores of the plurality of processor cores.