发明名称 |
Bitline deletion |
摘要 |
Embodiments relate to a computer system for bitline deletion, the system including a cache controller and cache. The system is configured to perform a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line, recording a second address of the second error, comparing first and second bitline addresses, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to the third bitline address and deleting a location corresponding to the third cache line based on the activated bitline delete mode and matching third and second bitline addresses. |
申请公布号 |
US9086990(B2) |
申请公布日期 |
2015.07.21 |
申请号 |
US201313788744 |
申请日期 |
2013.03.07 |
申请人 |
International Business Machines Corporation |
发明人 |
Ambroladze Ekaterina M.;Blake Michael A.;Fee Michael;Huynh Hieu T.;Meaney Patrick J.;O'Neill Arthur J. |
分类号 |
G06F11/00;G11C29/00;G06F11/10;G06F11/08;G06F11/07;G11C29/12 |
主分类号 |
G06F11/00 |
代理机构 |
Cantor Colburn LLP |
代理人 |
Cantor Colburn LLP ;McNamara Margaret |
主权项 |
1. A computer program product for bitline deletion, the computer program product comprising:
a tangible, non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: detecting a first error when reading a first cache line in an array within a cache; recording a first bitline address and a first wordline address of the first error in the first cache line; detecting a second error when reading a second cache line in the array within the cache; recording a second bitline address and a second wordline address of the second error in the second cache line; comparing the first bitline address to the second bitline address; comparing the first wordline address to the second wordline address; activating, by a cache controller, a bitline delete mode based on the first bitline address matching the second bitline address and the first wordline address not matching the second wordline address; detecting a third error when reading a third cache line in the array within the cache; recording a third bitline address of the third error in the third cache line; comparing the second bitline address to the third bitline address of the third cache line; and removing, by the cache controller, a location corresponding to the third cache line from available cache locations based on the bitline delete mode being activated and the third bitline address matching the second bitline address. |
地址 |
Armonk NY US |