发明名称 |
Apparatus to access multi-bank memory |
摘要 |
A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made. |
申请公布号 |
US9086959(B2) |
申请公布日期 |
2015.07.21 |
申请号 |
US201012902681 |
申请日期 |
2010.10.12 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Seo Woong;Ryu Soo-Jung;Kim Yoon-Jin;Cho Young-Chul;Park Il-Hyun;Oh Tae-Wook |
分类号 |
G06F12/10;G06F12/06;G06F3/06;G06F12/02 |
主分类号 |
G06F12/10 |
代理机构 |
NSIP Law |
代理人 |
NSIP Law |
主权项 |
1. A multi-bank memory access apparatus comprising:
a stride register configured to store stride values that correspond to a width of a frame memory; and an address converter configured to control access to a logical block within a multi-bank memory in row and column directions, the logical block having a width determined according to the stride values, wherein the address converter comprises
a two-dimensional address converter configured to convert the received memory access address into a two-dimensional address value on the logical block, anda bank selector configured to output a bank selection signal to select a bank from banks in the multi-bank memory, and an address value for the selected bank, using the two-dimensional address value, andwherein the bank selection signal is determined according to a sum of two-dimensional address values x and y converted by the two-dimensional address converter. |
地址 |
Suwon-si KR |