发明名称 Power module including leakage current protection circuit
摘要 A power module including a power device and a periphery circuit configured to suppress a leakage current in the power device. The periphery circuit includes a leakage current detection circuit configured to detect a leakage current from the power device and control operation of the power device based on a result of the detection. The leakage current detection circuit including an input terminal connected to the power device, a plurality of NMOS transistors, a plurality of PMOS transistors connected to the plurality of NMOS transistors, and a comparator.
申请公布号 US9088151(B2) 申请公布日期 2015.07.21
申请号 US201313737217 申请日期 2013.01.09
申请人 Samsung Electronics Co., Ltd. 发明人 Kim Ho-jung;Shin Jai-kwang;Chung U-in;Choi Hyun-sik
分类号 G05F3/02;G01F1/10;H02H9/02;H03K17/56;H03K17/16 主分类号 G05F3/02
代理机构 Harness, Dickey & Pierce, P.L.C. 代理人 Harness, Dickey & Pierce, P.L.C.
主权项 1. A power module comprising: a power device; and a periphery circuit configured to suppress a leakage current in the power device, the periphery circuit including a leakage current detection circuit configured to detect a leakage current from the power device and control operation of the power device based on a result of the detection, the leakage current detection circuit including an input terminal connected to the power device, a plurality of NMOS transistors, a plurality of PMOS transistors connected to the plurality of NMOS transistors, and only one comparator connected to the plurality of NMOS transistors and the plurality of PMOS transistors, wherein two NMOS transistors of the plurality of NMOS transistors are connected to the power device, and the two NMOS transistors of the plurality of NMOS transistors are connected to the only one comparator, the input terminal includes a first input terminal connected to a gate of the power device and a second input terminal connected to a source of the power device, and the first input terminal is connected to a gate of a first one of the two NMOS transistors, and the second input terminal is connected to a gate of a second one of the two NMOS transistors.
地址 Gyeonggi-do KR