Clocking scheme for reconfigurable wideband analog-to-digital converter

摘要

A clocking scheme for a reconfigurable wideband analog-to-digital converter (ADC) including a plurality of Delay Locked Loops (DLLs) arranged in parallel. Each DLL is responsive to an input clock signal and configured to selectively generate a plurality of output clock signals for controlling the operation of the ADC.

主权项

1. A clocking system for a reconfigurable wideband analog-to-digital converter (ADC) comprising:
a plurality of Delay Locked Loops (DLLs) arranged in parallel, each DLL responsive to an input clock signal and configured to generate a plurality of output clock signals for controlling the operation of the ADC; a DLL controller for selectively activating at least one of the plurality of DLLs and deactivating the remaining DLLs; and a clock edge control system for adjusting the phase of the plurality of output clock signals from the activated DLL.