Flash memory device reducing layout area

摘要

A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably.

主权项

1. A flash memory device comprising:
a memory array; a plurality of pairs of bit lines in communication with the memory array, each pair of bit lines comprising an even bit line and an odd bit line; a plurality of common bit lines, each common bit line corresponding to one of the plurality of pairs of bit lines; and a data transmission block in communication with the plurality of pairs of bit lines and the plurality of common bit lines to provide data extracted from the memory array by the plurality of pairs of bit lines to the common bit lines corresponding to the plurality of pairs of bit lines, the data transmission block comprising: a plurality of power connection portions, each power connection portion in communication with one of the plurality of pairs of bit lines and comprising an even power transistor in communication with an even bit line of a given pair of bit lines and controlled to connect the even bit line to a power voltage and an odd power transistor in communication with an odd bit line of the given pair of bit lines and to connect the odd bit line to the power voltage; a plurality of select connection portions configured, each select connection portion in communication with a given power connection portion and comprising an even select transistor in communication with an even bit line of the pair of bit lines associated with the given power connection and controlled to connect the associated even bit line to a given common bit line and an odd select transistor in communication with an odd bit line of the pair of bit lines associated with the given power connection and controlled to connect the associated odd bit line to the given common bit line; and a single common active region comprising all even power transistors and odd power transistors of at least two of the plurality of power connection portions and all even select transistors and odd select transistors of the plurality of select connection portions.