| 摘要 |
<p>A unit memory cell includes a high threshold voltage transistor and a regular threshold voltage translator. The high threshold voltage transistor comprises: a first node to receive entry data connected to an entry bit line, a second node to transmit entry data connected to a data node, a gate node which is connected to an entry word line, and a body bias voltage code in which a voltage level is controlled. The regular threshold voltage transistor comprises: a first node to receive read currents by being connected to a read bit line, a second node to transmit the read current by being connected to the read word line, a gate node connected to the data node, and the body bias voltage node in which the voltage level is controlled. According to the present invention, the unit memory cell may increase re-tension time and reduces a leaked current of the transistor by controlling the body bias voltage and the threshold voltage of the transistor.</p> |
