SRAM WRITE DRIVER WITH IMPROVED DRIVE STRENGTH

摘要

A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the gate. In this manner, the column select control is removed from the drive path, thus increasing drive strength. Further, a second semiconductor junction connects the gate of the single NMOS device in the drive path when the gate signal is interrupted.

主权项

1. A subsystem configured to perform write operations with memory cells, the subsystem comprising:
a first bit line driver configured to write a data bit to a memory cell and including:
a first circuit element that is gated by a first write select line and coupled to a first data line configured to transport the data bit,a second circuit element coupled to the first circuit element and gated by the first write select line, anda third circuit element that is coupled to the memory cell and gated by the first circuit element and the second circuit element and is configured to output the data bit to the memory cell upon activation of the first data line and the first write select line.