MAPPED FIFO BUFFERING

摘要

A network interface device for connection between a network and a data processing system, the network interface device comprising: an I/O interface for connection to a data processing system; a set of physical data ports for connection to a network; a unified memory comprising a plurality of buffers; a plurality of ingress ports operable to receive data packets for buffering at the unified memory, a first subset of the plurality of ingress ports being configured to receive data packets on a transmit path from said I/O interface, and a second subset of the plurality of ingress ports being configured to receive data packets on a receive path from said set of physical data ports; a memory manager configured to store representations of a plurality of virtual queues held in the unified memory, each virtual queue being a linked logical sequence of buffers of the unified memory; and an ingress interface configured to service the ingress ports in a predetermined order and write data packets received at the ingress ports to buffers of the unified memory selected by the memory manager; wherein the memory manager is arranged to select buffers of the unified memory so as to cause the ingress interface to populate the plurality of virtual queues with data packets, and the ingress interface is arranged to contiguously write data packets into the linked logical sequence of buffers representing each virtual queue.

主权项

1. A network interface device for connection between a network and a data processing system, the network interface device comprising:
an I/O interface for connection to a data processing system; a set of physical data ports for connection to a network; a unified memory comprising a plurality of buffers for buffering data packets directed to the data processing system before the data packets are provided to the I/O interface; a plurality of ingress ports operable to receive data packets directed to the data processing system, for buffering at the unified memory, a first subset of the plurality of ingress ports being configured to receive data packets on a transmit path from said I/O interface, and a second subset of the plurality of ingress ports being configured to receive data packets on a receive path from said set of physical data ports; a memory manager configured to store representations of a plurality of virtual queues held in the unified memory, each virtual queue being a linked logical sequence of buffers of the unified memory; and an ingress interface configured to service the ingress ports in a predetermined order and write data packets received at the ingress ports to buffers of the unified memory selected by the memory manager;wherein the memory manager is arranged to select buffers of the unified memory so as to cause the ingress interface to populate the plurality of virtual queues with data packets, and the ingress interface is arranged to contiguously write data packets into the linked logical sequence of buffers representing each virtual queue.