发明名称 CHANNEL CODING METHOD OF VARIABLE LENGTH INFORMATION USING BLOCK CODE
摘要 A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.
申请公布号 US2015200687(A1) 申请公布日期 2015.07.16
申请号 US201514639805 申请日期 2015.03.05
申请人 LG ELECTRONICS INC. 发明人 ROH Dong Wook;AHN Joon Kui;YU Nam Yul;CHO Jung Hyun;NOH Yu Jin;KIM Ki Jun;LEE Dae Won
分类号 H03M13/37;H04L5/00;H04W72/04;H04L1/00 主分类号 H03M13/37
代理机构 代理人
主权项 1. A method for channel-coding input bits, the method comprising: channel-coding the input bits by using a block code, wherein the block code includes basis sequences Mi,0 to Mi,10 defined in a following Table 1:TABLE 1iMi,0Mi,1Mi,2Mi,3Mi,4Mi,5Mi,6Mi,7Mi,8Mi,9Mi,100110000000011111000000112100100101113101100001014111100010015110010111016101010101117100110011018110110010119101110100111010100111011111110011010112100101011111311010101011141000110100115110011110111611101110010171001110010018110111110001910000110000201010001000121110100000112210001001101231110100011124111110111102511000111001261011010011027111101011102810101110100291011111110030111111111113110000000000,and wherein channel-coding the input bits comprises: multiplying the input bits a0, a1, a2, a3, . . . , aA-1 by the basis sequences Mi,0, Mi,1, Mi,2, Mi,3, . . . , Mi,A-1 defined in the Table 1, respectively; andapplying a modulo-2 operation to a sum of the multiplied input bits a0*Mi,0, a1*Mi,1, a2*Mi,2, a3*Mi,3, . . . , aA-1*Mi,A-1.
地址 Seoul KR