发明名称 |
TRANSISTOR DESIGN |
摘要 |
Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type. |
申请公布号 |
US2015200253(A1) |
申请公布日期 |
2015.07.16 |
申请号 |
US201414156546 |
申请日期 |
2014.01.16 |
申请人 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
发明人 |
Chen Wen-Yuan;Yu Tsung-Hsing;Goto Ken-Ichi;Wu Zhiqiang |
分类号 |
H01L29/10;H01L29/66;H01L29/417;H01L29/167;H01L29/16;H01L29/165;H01L21/02;H01L21/265;H01L29/78;H01L29/36 |
主分类号 |
H01L29/10 |
代理机构 |
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代理人 |
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主权项 |
1. A transistor device formed on a semiconductor substrate, comprising:
a recess disposed within a transistor region of the semiconductor substrate, and having a bottom surface that is lower than an upper surface of the semiconductor substrate, wherein the transistor region is doped with dopant impurities of a first impurity type; a channel region comprising:
a delta-doped layer comprising dopant impurities of the first impurity type;a layer of carbon-containing material overlying the delta-doped layer and confined to the recess; anda layer of semiconductor material overlying the layer of carbon-containing material and confined to the recess; a gate structure disposed over the layer of semiconductor material; and a source region and a drain region laterally spaced on opposing sides of the channel region. |
地址 |
Hsin-Chu TW |