| 发明名称 |
ELECTRONIC DEVICE, SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SAME |
| 摘要 |
A semiconductor package includes a substrate; a first semiconductor chip disposed on a first surface of the substrate, the first semiconductor chip either the only semiconductor chip disposed on the first surface of the substrate or a bottom-most semiconductor chip formed on the first surface of the substrate; a plurality of external connection terminals disposed on a second surface of the substrate that is opposite to the first surface of the substrate; a stress buffer layer formed on the first surface of the substrate to vertically overlap at least one of the plurality of external connection members, wherein the stress buffer layer is formed on an edge part of the substrate and does not contact or vertically overlap the first semiconductor chip; and a sealing member covering the first chip and the stress buffer layer. |
| 申请公布号 |
US2015200186(A1) |
申请公布日期 |
2015.07.16 |
| 申请号 |
US201414568113 |
申请日期 |
2014.12.12 |
| 申请人 |
Park Jin-woo |
发明人 |
Park Jin-woo |
| 分类号 |
H01L25/065;H01L23/00;H01L23/31;H01L23/48 |
主分类号 |
H01L25/065 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor package comprising:
a substrate; a first semiconductor chip disposed on a first surface of the substrate, the first semiconductor chip either the only semiconductor chip disposed on the first surface of the substrate or a bottom-most semiconductor chip formed on the first surface of the substrate; a plurality of external connection terminals disposed on a second surface of the substrate that is opposite to the first surface of the substrate; a stress buffer layer formed on the first surface of the substrate to vertically overlap at least one of the plurality of external connection members, wherein the stress buffer layer is formed on an edge part of the substrate and does not contact or vertically overlap the first semiconductor chip; and a sealing member covering the first chip and the stress buffer layer. |
| 地址 |
Seoul KR |
