BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS

摘要

Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI/PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI/PO.

主权项

1. A method of laying out a circuit design for an integrated circuit comprising:
receiving a description of the circuit design which includes a plurality of latches interconnected with at least one primary input and at least one primary output, by executing first instructions in a computer system; designating a subset of latches as boundary latches, by executing second instructions in the computer system; applying one or more placement constraints to the boundary latches, by executing third instructions in the computer system; performing global placement on the circuit design using wirelength optimization while maintaining the placement constraints applied to the boundary latches, by executing fourth instructions in the computer system; implementing timing assertions for the circuit design, by executing sixth instructions in the computer system; and running a timing driven placement on the circuit design subject to the timing assertions, by executing seventh instructions in the computer system.