Field Effect Transistor Constructions And Memory Arrays

摘要

In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers.

主权项

1. A vertical field effect transistor construction comprising:
a vertically-oriented stack comprising, in ascending order, a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region; the stack having a vertical sidewall; the vertical sidewall having a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region; third insulative material along an entirely of the middle portion of the vertical sidewall; a channel region material along the third insulative material and spaced from the conductive gate by the third insulative material; the channel region material being directly against at least part of the bottom portion of the vertical sidewall, and being directly against at least part of the top portion of the vertical sidewall; and the channel region material having a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å.