TIMING ADJUSTMENT CIRCUIT, CLOCK GENERATION CIRCUIT, AND METHOD FOR TIMING ADJUSTMENT

摘要

A timing adjustment circuit includes a detection unit to generate a detection signal in response to a first clock having a duty cycle of 50% and a first frequency, a second clock having a duty cycle of 50% and a second frequency that is half the first frequency, and a third clock having a duty cycle of 50%, the second frequency, and a phase displacement of 90 degrees relative to the second clock, the detection signal indicating timing relationship between the first clock and the second and third clocks, a low-pass filter to receive the detection signal, and a variable-delay circuit to adjust relative timing relationship between the first clock and the second clock in response to an output of the low-pass filter such that a center point of a pulse of the first clock is aligned with a center point of a pulse of the second clock.

主权项

1. A timing adjustment circuit, comprising:
a detection unit configured to generate a detection signal in response to a first clock signal having both a duty cycle of 50% and a first frequency, a second clock signal having both a duty cycle of 50% and a second frequency that is half the first frequency, and a third clock signal having both a duty cycle of 50% and the second frequency and having a phase displacement of 90 degrees relative to the second clock signal, the detection signal being indicative of timing relationship between the first clock signal and the second and third clock signals; a low-pass filter configured to receive the detection signal generated by the detection unit; and a variable-delay circuit configured to adjust a relative timing relationship between the first clock signal and the second clock signal in response to an output of the low-pass filter such that a center point of a pulse of the first clock signal is aligned with a center point of a pulse of the second clock signal.