Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory

摘要

A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping between the select gates and the dummy storage elements.

主权项

1. A method for performing an erase iteration of an erase operation, comprising:
in a first time period, increasing an erase voltage of a substrate while floating a voltage of a control gate of a first select gate transistor, driving a voltage of a control gate of a first non-user data non-volatile storage element and driving a voltage of a control gate of a second non-user data non-volatile storage element, wherein the first non-user data non-volatile storage element and the second non-user data non-volatile storage element are in a string of series-connected non-volatile storage elements which is formed on the substrate, the string comprises a plurality of user data non-volatile storage elements, and the first non-user data non-volatile storage element and the second non-user data non-volatile storage element are between the first select gate transistor and the plurality of user data non-volatile storage elements; in a second time period after the first time period, increasing the erase voltage of the substrate while floating the voltage of the control gate of the first select gate transistor and the voltage of the control gate of the first non-user data non-volatile storage element while driving the voltage of the control gate of the second non-user data non-volatile storage element; and in a third time period after the second time period, increasing the erase voltage of the substrate while floating the voltage of the control gate of the first select gate transistor, the voltage of the control gate of the first non-user data non-volatile storage element and the voltage of the control gate of the second non-user data non-volatile storage element.