| 摘要 |
A packet parsing engine 400 comprises a DMEM 402 configured to store packet data received from an assembly buffer; one or more registers in register groups 404, 406 configured to store parsing instructions or parse results; and one or more arithmetic logic units, ALU, 410 configured to parse the packet data based on the parsing instructions and to derive the parse results. The engine may be one engine of a plurality of engines configured to access a shared memory, and the engine may be configured to receive data from the shared memory or to send data to the shared memory. Each engine can be in one of a plurality of states. The plurality of states of an engine includes an allocated state, a processing state, and an idle state. Registers in register group 404 are utilized as scratch pads for storing intermediary information. Registers in register group 406 store parse results. Instruction decoder 412 may transmit information or signals to one or more multiplexers in engine 400. Further, instructions derived from decoder 412 may control the read or write operations of the registers and the operations by ALU 410. In various embodiments, instructions cause data being read from one or more registers, data being passed to ALU 410, or results being loaded into one or more registers. The DMEM may be divided into subsections, and at least one of the one or more registers may be divided into subsections, and the subsections may be configured such that while a DMEM subsection and its corresponding register subsection is parsing packet data for a first packet, one or more other subsections load packed data or unload parse results for a second packet. |
