发明名称 |
PULSED LASER ANNEAL PROCESS FOR TRANSISTORS WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN |
摘要 |
A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth. |
申请公布号 |
US2015200301(A1) |
申请公布日期 |
2015.07.16 |
申请号 |
US201514667544 |
申请日期 |
2015.03.24 |
申请人 |
Intel Corporation |
发明人 |
Jensen Jacob;GHANI Tahir;LIU Mark Y.;KENNEL Harold;JAMES Robert |
分类号 |
H01L29/78;H01L29/165;H01L29/417;H01L29/08;H01L29/10 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
1. A non-planar transistor, comprising:
a semiconductor fin including a channel region disposed below a gate stack; and raised semiconductor source/drains coupled to the channel region and disposed on opposite ends of the fin with the gate stack disposed there between, wherein the raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth, the super-activated dopant region having a higher activated dopant concentration than the activated dopant region. |
地址 |
Santa Clara CA US |