发明名称 |
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE |
摘要 |
A method of manufacturing a semiconductor device is provided. The method includes forming a fin structure on a semiconductor substrate and forming a well region in the semiconductor substrate by ion implantation so as to form transistors. The transistors include a pull-up transistor, a transfer gate transistor, and a pull-down transistor of a SRAM cell. The ion implantation is used to adjust threshold voltages of the transistors. Standard threshold voltage (SVt) ion implantation conditions are used to adjust a threshold voltage of the pull-up transistor and a threshold voltage of the transfer gate transistor, and low threshold voltage (LVt) ion implantation conditions are used to adjust a threshold voltage of the pull-down transistor. |
申请公布号 |
US2015200194(A1) |
申请公布日期 |
2015.07.16 |
申请号 |
US201514591716 |
申请日期 |
2015.01.07 |
申请人 |
Semiconductor Manufacturing International (Shanghai) Corporation |
发明人 |
JU Jianhua;ZHANG Shuai |
分类号 |
H01L27/11;H01L29/66 |
主分类号 |
H01L27/11 |
代理机构 |
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代理人 |
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主权项 |
1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure on a semiconductor substrate; and forming a well region in the semiconductor substrate by ion implantation so as to form transistors, wherein the transistors include a pull-up (PU) transistor, a transfer gate (PG) transistor, and a pull-down (PD) transistor of a static random-access memory (SRAM) cell; the ion implantation being used to adjust threshold voltages of the transistors, wherein standard threshold voltage (SVt) ion implantation conditions are used to adjust a threshold voltage of the PU transistor and a threshold voltage of the PG transistor, and low threshold voltage (LVt) ion implantation conditions are used to adjust a threshold voltage of the PD transistor. |
地址 |
Shanghai CN |