| 摘要 |
<p>The present invention includes a semiconductor pin which is formed on a semiconductor substrate and includes a first source and drain region, a second source and drain region, and a channel region, a gate electrode which crosses the surface of the channel region and is formed on the semiconductor substrate, a gate dielectric layer which is located between the gate electrode and the channel region, a contact plug which is in contact with the first source and drain region and the second source and drain region, and an insulation spacer with a multilayer structure to cover both sidewalls of the gate electrode. The insulation spacer includes an air spacer.</p> |
