| 摘要 |
<p>A synchronizer circuit 200 comprises a first flip-flop operated with a first clock signal C1, the first flip-flop being configured to read a data item at a first sampling point correlating with a first edge of a first edge type of the first clock signal, a second flip-flop in the second clock signal domain, the second flip-flop being configured to read the data item from the first flip-flop at a read-out sampling point, and a finite state machine coupled to the second flip-flop, the finite state machine being configured to select a second sampling point as the read-out sampling point of the second flip-flop, wherein the second sampling point correlates with a second edge of the first edge type of a second clock signal, which second edge directly follows the first edge, if the time interval between the occurrence of the first edge and the second edge is greater than a predeterminable threshold, and the finite state machine being configured to select a third sampling point as the read-out sampling point of the second flip-flop, wherein the third sampling point correlates with a third edge of a second edge type of the second clock signal, which third edge directly follows the second edge, if the time interval between the occurrence of the first edge and the second edge is smaller than or equal to a predeterminable threshold.</p> |
