发明名称 異種マルチコアシステム用のダイナミックコア選択
摘要 Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
申请公布号 JP5750172(B2) 申请公布日期 2015.07.15
申请号 JP20130557709 申请日期 2011.12.28
申请人 インテル・コーポレーション 发明人 ウー、ユーフェン;フー、シーリアン;ボリン、エドソン;ワン、チェン
分类号 G06F9/50 主分类号 G06F9/50
代理机构 代理人
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