Read assist circuit for an SRAM, including a word line suppression circuit

摘要

A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving the array supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a first switch coupled in series and a second switch. The switches are responsive to a control signal. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

主权项

1. A memory circuit comprising:
a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving the array supply voltage; and a word line suppression circuit coupled to the word line, having a PMOS transistor coupled to the word line, and a diode and an NMOS transistor coupled in series, the diode coupled to the word line, the NMOS transistor and the PMOS transistor being responsive to a control signal.