发明名称 Fabrication methods of integrated semiconductor structure
摘要 An integrated circuit device and method for manufacturing an integrated circuit device is disclosed. The integrated circuit device comprises a core device and an input/output circuit. Each of the core device and input/output circuit includes a PMOS structure and an NMOS structure. Each of the PMOS includes a p-type metallic work function layer over a high-k dielectric layer, and each of the NMOS structure includes an n-type metallic work function layer over a high-k dielectric layer. There is an oxide layer under the high-k dielectric layer in the input/output circuit.
申请公布号 US9082789(B2) 申请公布日期 2015.07.14
申请号 US201113107636 申请日期 2011.05.13
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 Huang Chun-Hung;Lin Yu-Hsien;Lin Ming-Yi;Chen Jyh-Huei
分类号 H01L21/8234;H01L29/66;H01L21/8238;H01L29/165;H01L29/78;H01L21/28;H01L29/49;H01L29/51 主分类号 H01L21/8234
代理机构 Lowe Hauptman & Ham, LLP 代理人 Lowe Hauptman & Ham, LLP
主权项 1. A method comprising: providing a substrate having a first region and a second region; forming a first dielectric layer of a first material over the substrate in the first region; forming a second dielectric layer of a second material over the substrate in the second region, wherein the second material is different from the first material; forming a sacrificial gate layer over the first and second dielectric layers; patterning the sacrificial gate layer, the first and second dielectric layers to form gate stacks in the first and the second regions; forming an ILD layer over the gate stacks in the first and second regions; partially removing the ILD layer in the first and second regions to expose the sacrificial gate layer; removing the exposed sacrificial gate layer to define openings in the ILD layer in the first and second regions and expose the first dielectric layer and the second dielectric layer; and removing the second dielectric layer exposed in at least one of the openings in the ILD layer, removing the second dielectric layer comprising initiating an etching process on the exposed first dielectric layer and the exposed second dielectric layer, the etching process having high etching selectivity between the second dielectric layer and the first dielectric layer.
地址 TW
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