Circuit structure for providing conversion gain of a pixel array

摘要

Techniques and mechanisms for a pixel array to provide a level of conversion gain. In an embodiment, the pixel array includes conversion gain control circuitry to be selectively configured at different times for different operational modes, each mode for implementing a respective conversion gain. The conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—a supply voltage. In another embodiment, the conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—sample and hold circuitry.

主权项

1. A pixel array comprising:
a pixel cell including a source follower transistor and a row select transistor; a first trace coupled to the source follower transistor; a second trace to receive from the row select transistor an output of the pixel cell; switch circuitry including:
a first transistor coupled to a supply voltage and the source follow transistor, wherein the first transistor is coupled to the source follower transistor via a first portion of the first trace;a second transistor coupled to a sample and hold circuit and the source follow transistor, wherein the second transistor is coupled to the source follower transistor via a second portion of the first trace;a third transistor coupled to the supply voltage and the row select transistor, wherein the third transistor is coupled to the row select transistor via a first portion of the second trace; anda fourth transistor coupled to the sample and hold circuit and the row select transistor, wherein the fourth transistor is coupled to the row select transistor via a second portion of the second trace;the switch circuitry to transition between a first operational mode and a second operational mode based on a control signal, the first operational mode including the first transistor and the fourth transistor each being in a respective active state and the second transistor and the third transistor each being in a respective inactive state, the second operational mode including the first transistor and the fourth transistor each being in a respective inactive state and the second transistor and the third transistor each being in a respective active state.