发明名称 Subsonic test signal generation technique
摘要 An apparatus includes a capacitor, a current generating circuit communicatively coupled to the capacitor, and a current pulse timing circuit communicatively coupled to the current source circuit. The current timing pulse circuit is configured to time durations of a first plurality of current pulses from the current generating circuit for charging the capacitor and a second plurality of current pulses for discharging the capacitor, and step the durations of the current pulses between a minimum duty cycle and a maximum duty cycle. A cycle of providing the first plurality of current pulses and providing the second plurality of current pulses results in generation of a subsonic pseudo-sinusoidal pulse signal at the capacitor.
申请公布号 US9083322(B2) 申请公布日期 2015.07.14
申请号 US201113180801 申请日期 2011.07.12
申请人 Fairchild Semiconductor Corporation 发明人 Llewellyn William D.
分类号 H03B28/00;H03K4/02 主分类号 H03B28/00
代理机构 Schwegman Lundberg & Woessner, P.A. 代理人 Schwegman Lundberg & Woessner, P.A.
主权项 1. An apparatus comprising: a capacitor; a current generating circuit communicatively coupled to the capacitor; and a current pulse timing circuit communicatively coupled to the current generating circuit and configured to time durations of a first plurality of current pulses from the current generating circuit for charging the capacitor and a second plurality of current pulses for discharging the capacitor, and step the durations of the current pulses between a minimum duty cycle and a maximum duty cycle, wherein the current pulse timing circuit is configured to increase the current pulse durations from the minimum duty cycle to the maximum duty cycle and decrease the current pulse duration from the maximum duty cycle to the minimum duty cycle during each of the first and second plurality of current pulses, wherein the current pulse timing circuit includes: an up/down counter circuit configured to count from a minimum count to a maximum count and back to the minimum count for each of the first and second plurality of current pulses; and a pulse generation counter circuit configured to time a current pulse duration according to a count of the up/down counter circuit, and wherein a cycle of providing the first plurality of current pulses and providing the second plurality of current pulses results in generation of a pseudo-sinusoidal pulse signal at the capacitor.
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