发明名称 Bit line and compare voltage modulation for sensing nonvolatile storage elements
摘要 In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed.
申请公布号 US9082502(B2) 申请公布日期 2015.07.14
申请号 US201314051416 申请日期 2013.10.10
申请人 SANDISK TECHNOLOGIES INC. 发明人 Dunga Mohan V.;Higashitani Masaaki
分类号 G11C16/04;G11C16/34;G11C11/56 主分类号 G11C16/04
代理机构 Vierra Magen Marcus LLP 代理人 Vierra Magen Marcus LLP
主权项 1. A method for operating non-volatile storage, comprising: applying a first set of one or more bit line voltages to a plurality of bit lines; verifying programming for non-volatile storage elements connected to a first set of word lines and the plurality of bit lines in response to the first set of one or more bit line voltages; applying a second set of one or more bit line voltages to the plurality of bit lines, the first set of one or more bit line voltages are lower than the second set of one or more bit line voltages; verifying programming for non-volatile storage elements connected to a second set of word lines and the plurality of bit lines in response to the second set of one or more bit line voltages, the non-volatile storage elements connected to the first set of word lines are programmed prior to programming of the non-volatile storage elements connected to the second set of word lines after a common erasing, the non-volatile storage elements connected to the first set of word lines and the non-volatile storage elements connected to the second set of word lines are in a common block; applying one or more read bit line voltages to the plurality of bit lines; and reading the non-volatile storage elements connected to the first set of word lines and the plurality of bit lines in response to the one or more read bit line voltages, either the verifying programming for non-volatile storage elements connected to the first set of word lines or the reading the non-volatile storage elements connected to the first set of word lines includes applying a compare voltage to a selected word line for a data state on the first set of word lines that is different than another compare voltage for the data state used for non-volatile storage elements connected to the second set of word lines.
地址 Plano TX US