发明名称 Static NAND cell for ternary content addressable memory (TCAM)
摘要 A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.
申请公布号 US9082481(B2) 申请公布日期 2015.07.14
申请号 US201414503861 申请日期 2014.10.01
申请人 QUALCOMM Incorporated 发明人 Terzioglu Esin;Desai Nishith;Vattikonda Rakesh;Jung ChangHo;Yoon Sei Seung
分类号 G11C15/04;G11C15/00 主分类号 G11C15/04
代理机构 代理人 Holdaway Paul S.
主权项 1. A static, ternary content addressable memory (TCAM), comprising: a first means for generating a comparison output based on a comparison of a search bit to a key bit, wherein a first pull-down transistor conducts and a first pull-up transistor does not conduct in response to the comparison output indicating a match between the search bit and the key bit, and wherein the first pull-down transistor does not conduct and the first pull-up transistor conducts in response to the comparison output indicating a mismatch between the search bit and the key bit; a second means for generating a mask output, wherein a second pull-down transistor conducts and a second pull-up transistor does not conduct in response to the mask output being asserted, and wherein the second pull-down transistor does not conduct and the second pull-up transistor conducts in response to the mask output being de-asserted, the first pull-down transistor and the second pull-down transistor being connected in parallel between a match line output and a first supply voltage terminal, and the first pull-up transistor and the second pull-up transistor being connected in series between a second supply voltage terminal and the match line output.
地址 San Diego CA US