发明名称 Systems, processes and computer-accessible medium for providing logic encryption utilizing fault analysis
摘要 Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.
申请公布号 US9081929(B2) 申请公布日期 2015.07.14
申请号 US201313735642 申请日期 2013.01.07
申请人 New York University 发明人 Sinanoglu Ozgur;Pino Youngok;Rajendran Jeyavijayan;Karri Ramesh
分类号 G06F17/50;H03K19/003 主分类号 G06F17/50
代理机构 Andrews Kurth LLP 代理人 Andrews Kurth LLP
主权项 1. A process for encrypting a circuit, including: determining at least one location to insert at least one gate in the circuit using a fault analysis procedure that identifies a number of outputs affected by the at least one location; and encrypting the circuit by inserting the at least one gate, with one input of the at least one gate controlled by at least one key input bit, in at least one section of the at least one location.
地址 New York NY US